Progress update on my Cray-1

Despite my lack of website updates, I actually have continued work on my Cray-1 project. In addition to some progress in recovering an operating system for it, I’ll (hopefully) be releasing another hardware update pretty soon. Major new features that seem to be mostly working:

- I/O channels! I actually implemented the I/O channel hardware for the Cray-1. Initially I had just been using memory-mapped hardware for everything, but I’d like to actually use that space for memory in the near future, so I took some time to add real DMA hardware. 12 Input and 12 Output channels (I think they were typically used in pairs as 12 full-duplex I/O channels for connecting devices). As currently implemented, they’re 64-bit I/O ports that can have anything hung off of them. The 64-bit UART the Cray currently uses for I/O, for instance, would be straightforward to connect to a pair of channels.

-New memory controller / arbiter! This goes along with the I/O channels, as I now have 24 I/O channels competing for memory access, in addition to the main memory controller and the Instruction Buffer. For now it’s just a simple priority arbiter, although I intend to make it a round-robin type to make it more useful. I also had to completely mangle the timing of the main CPU memory ‘functional unit’ to support the new arbiter. The performance impact will probably be minimal. Hopefully I can get around to adding a full 4-megaword (32 megabyte) complement of memory to the Cray soon via on-board DRAM.

-New hardware! I retired the Spartan-3E 1600 I had been using (which was too small to support the I/O channel hardware, unfortunately), and moved to a new Spartan-6 LX45t board that Xilinx sent me. This gave me a lot more breathing room for implementing extra features (hopefully including the aforementioned DRAM controller soon), as well as 128MB of on-board DDR3 memory.

-More speed! I’m fortunately much better at RTL design now than when I started this project, so I took some time to look at what the actual critical path was that was holding me back to 33 MHz or so. With a bit of tweaking I’m actually able to get my design to compile for the Spartan-6 at the Cray-1′s original 80 MHz! This is something that had really been nagging me, so I was pretty happy to get that working.

-A new UART! I moved to a new UART from opencores.org that supports RTS/CTS handshaking, so I can get faster data transfers from my main PC to the Cray-1 (115200 kbps for now – I haven’t tried it any faster).

I probably introduced a whole pile of new bugs with my timing fixes (any DV engineers out there looking for a new hobby?), but I was able to write a simple test program that listens on the serial port and echoes whatever I type back to me (running at 80MHz!!).

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